1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a shallow trench isolation.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, the local oxidation of silicon (LOCOS) technique is widely utilized in semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quite a period of time, it is of the most reliable and low-cost methods for fabricating device isolation region. However, there are still some drawbacks to LOCOS. The drawbacks include internal stress generation and bird's beak encroachment. For a highly integrated device, the problem of bird's beak encroachment by isolation regions is especially difficult to avoid; thus the isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is the other conventional method of forming isolation regions. Shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate, and then depositing an oxide layer in the trench and on the substrate. Next, a chemical-mechanical polishing step is used to planarize the oxide layer and to form an STI region. Therefore, the problem induced by the bird's beak can be overcome. As line width becomes smaller and integration becomes higher, STI is an ideal and scaleable isolation technique.
FIGS. 1A through ID are schematic, cross-sectional views of the conventional process for manufacturing STI.
As shown in FIG. 1A, a pad oxide layer 102 and a silicon nitride layer 104 are formed over the substrate 100 in sequence. A trench 106 is formed in the substrate 100 by patterning the silicon nitride layer 104, the pad oxide layer 102 and the substrate 100.
As shown in FIG. 1B, a liner oxide 108 is formed on the sidewall and the base surface of the trench 106.
In FIG. 1C, a silicon oxide layer (not shown) is formed over the substrate 100 and fills the trench 108. Chemical-mechanical polishing is used to planarize the silicon oxide layer until the silicon nitride layer is exposed and an STI I 18 is formed.
As shown in FIG. 1D, the silicon nitride layer 104 and the pad oxide layer 102 are stripped away to expose the surface of the substrate 100.
Since the materials of the STI 118 and the pad oxide layer 102 are the same, a portion of the exposed portion of the STI 118 is stripped away while the pad oxide layer 102 is being stripping away. Therefore, portions of the sidewall and the top face of the STI 118 are stripped away and a recess 120 is present in the STI 118 at the top corner 110 of the trench 106. The recess 120 leads to a kink effect of the FETs. Moreover, when the gate structure is subsequently formed over the substrate 100, some gate material is usually left in the recess 120. In order to avoid the leakage caused by the residual gate material in the recess 120, it is necessary to perform an over-etching step to clean the residues from the recess 120.